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usr /
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powerpc64le-linux-gnu /
asm /
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auxvec.h
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bitsperlong.h
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bootx.h
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bpf_perf_event.h
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byteorder.h
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cputable.h
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eeh.h
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elf.h
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epapr_hcalls.h
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errno.h
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fcntl.h
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ioctl.h
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ioctls.h
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ipcbuf.h
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kvm.h
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kvm_para.h
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mman.h
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msgbuf.h
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nvram.h
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opal-prd.h
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papr-miscdev.h
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papr-sysparm.h
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papr-vpd.h
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param.h
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perf_event.h
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perf_regs.h
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poll.h
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posix_types.h
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ps3fb.h
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ptrace.h
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resource.h
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sembuf.h
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setup.h
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shmbuf.h
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sigcontext.h
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siginfo.h
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signal.h
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socket.h
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sockios.h
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spu_info.h
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stat.h
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statfs.h
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swab.h
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termbits.h
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termios.h
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tm.h
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types.h
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ucontext.h
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unistd.h
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unistd_32.h
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unistd_64.h
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vas-api.h
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Code Editor : auxvec.h
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _ASM_POWERPC_AUXVEC_H #define _ASM_POWERPC_AUXVEC_H /* * We need to put in some extra aux table entries to tell glibc what * the cache block size is, so it can use the dcbz instruction safely. */ #define AT_DCACHEBSIZE 19 #define AT_ICACHEBSIZE 20 #define AT_UCACHEBSIZE 21 /* A special ignored type value for PPC, for glibc compatibility. */ #define AT_IGNOREPPC 22 /* The vDSO location. We have to use the same value as x86 for glibc's * sake :-) */ #define AT_SYSINFO_EHDR 33 /* * AT_*CACHEBSIZE above represent the cache *block* size which is * the size that is affected by the cache management instructions. * * It doesn't nececssarily matches the cache *line* size which is * more of a performance tuning hint. Additionally the latter can * be different for the different cache levels. * * The set of entries below represent more extensive information * about the caches, in the form of two entry per cache type, * one entry containing the cache size in bytes, and the other * containing the cache line size in bytes in the bottom 16 bits * and the cache associativity in the next 16 bits. * * The associativity is such that if N is the 16-bit value, the * cache is N way set associative. A value if 0xffff means fully * associative, a value of 1 means directly mapped. * * For all these fields, a value of 0 means that the information * is not known. */ #define AT_L1I_CACHESIZE 40 #define AT_L1I_CACHEGEOMETRY 41 #define AT_L1D_CACHESIZE 42 #define AT_L1D_CACHEGEOMETRY 43 #define AT_L2_CACHESIZE 44 #define AT_L2_CACHEGEOMETRY 45 #define AT_L3_CACHESIZE 46 #define AT_L3_CACHEGEOMETRY 47 #define AT_MINSIGSTKSZ 51 /* stack needed for signal delivery */ #define AT_VECTOR_SIZE_ARCH 15 /* entries in ARCH_DLINFO */ #endif
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